Semiconductor Engineering

Automatic Layout Generator Targeting Region-based Layouts for Advanced FinFET-Based Full-Custom Circuits (UT Austin/NVIDIA)

A technical paper titled “AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies” was published by researchers at UT Austin and NVIDIA. “This paper presents AutoCRAFT, an ...
Nasdaq

TSMC Certifies Synopsys' Digital and Custom Design Platforms on TSMC 5nm FinFET Process Technology

IC Compiler II and Design Compiler Graphical provide a complete digital implementation flow delivering optimized power, performance, area, and full via pillar support StarRC, PrimeTime, NanoTime, and ...
Semiconductor Engineering

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of ...
EDN

Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced delivery of a comprehensive design ...
Electronic Design

Identifying transistor-level yield limiters in the FinFET era

As the digital semiconductor manufacturing process moves into the FinFET era, more and more front-end-of-line (FEOL) defects are observed due to extremely small feature size and complex manufacturing ...
Design And Reuse

High-Speed SerDes Design: Architecture, Equalization, and CDR Circuits

High-Speed Serializer/Deserializer (SerDes) technology addresses these challenges by enabling efficient communication over ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
NextBigFuture

finFETs Could be Smaller and at least Five Times Faster than silicon Transistors

Researchers are making progress in developing new types of transistors, called finFETs, which use a finlike structure instead of the conventional flat design, possibly enabling engineers to create ...
Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
Design-Reuse

UMC Announces Release of 14nm eHV FinFET Platform, Advancing Innovation in Next-Generation Smartphone Displays

HSINCHU, Taiwan — United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a leading global semiconductor foundry, today announced the release of its 14nm embedded high-voltage (eHV) ...
EDN

Samsung and partners create 14nm FinFET test chips

Over the past couple of days there have been a string of press releases related to the tape-out of a test chip from Samsung at 14nm using FinFETs. This is a condensation of those releases from Samsung ...