EDN

ITC: DeFacTo unveils DFT product that eliminates need for gate-level scan

DeFacTo Technologies announced at the International Test Conference a new DFT product that analyzes a register-transfer level (RTL) integrated-circuit design, creates appropriate RTL scan-test ...
Design-Reuse

Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC

With advanced technology nodes, the SoCs are growing in density and gate count. This creates challenges regarding the testability, and more importantly, the test cost. The design complexity and size ...
Semiconductor Engineering

No-Compromise Packetized Test Improves DFT Efforts

Design for Test (DFT) managers often must make difficult and sometimes costly trade-offs between test implementation effort and manufacturing test cost. The traditional method for evaluating these ...
EDN

Optimizing compression in scan-based ATPG DFT implementations

In the 1990s, Carnegie Mellon researchers created a comprehensive scan-test cost model that demonstrated how design for test (DFT) contributes to profitability (Ref. 1). With scan compression in wide ...
Design-Reuse

SynTest Receives "Multiple-capture DFT system for scan-based integrated circuits" Patent for At-Speed Scan/BIST Invention

SAN JOSE, Calif., Oct 19, 2005-- SynTest Technologies, Inc., a leading supplier of Design-for-Test (DFT) tools, was granted 33 claims on Oct. 11, 2005 under United States Patent # 6,954,887 for its ...
Semiconductor Engineering

DFT At The Leading Edge

Experts at the Table: Semiconductor Engineering sat down to discuss the rapidly changing landscape of design for testability (DFT), focusing on the impact of advancements in fault models, high-speed ...